Integrated circuit memory devices are widely used for consumer and commercial applications. One commonly used non-volatile memory device is a flash memory device. In general, cell arrays of flash memory devices include a plurality of cell transistors. Each of the cell transistors is selected by word lines and bit lines. Source regions of a plurality of cell transistors are electrically connected to each other. The source regions are connected by a common source line. In order to reduce the resistance of the common source line, the common source line includes source strapping regions formed at regular intervals, and a strapping line having high conductivity is connected to the source strapping regions.
FIGS. 1A and 1B show a cell array of a conventional NOR-type flash memory device.
Referring to FIGS. 1A and 1B, a plurality of active regions 10 and 12, defined by a device isolation layer, are formed on a semiconductor substrate. A plurality of word lines WL cross over the active regions 10 and 12. Two adjacent word lines WL provide word line pairs WP. Source regions 14 are formed in active regions 10 between the two word lines of the word line pairs WP. The source regions 14 are electrically connected by a common source line CSL. Drain regions 16 are formed in the active regions 10 between adjacent word line pairs WP. A device isolation layer between the two word lines of the word line pairs WP is removed, so that it is absent. As a result, the common source line CSL electrically connects a plurality of active regions 10 and 12.
Drain contacts BC are connected to the drain regions 16, and source contacts SC are connected to the common source line CSL at regular intervals, respectively. In order to increase integration, the width of the common source line CSL may be narrower than that of the drain region. Accordingly, a region for forming the source contact SC may be desired. In order to form the source contact SC, the common source line CSL includes a wider region that is provided at regular intervals. The wider region corresponds to a source strapping region SR. The word lines WL are bent adjacent the source strapping region SR so that a region where the source contact SC will be formed may be secured.
When a memory device has relatively low integration, the pitch of the active regions can be large. As a result, there may be little or no degradation of adjacent cell transistors when the word lines WL are bent in the source strapping region SR. Accordingly, the active regions 10 and 12 may be formed at regular intervals. However, as the integration of the memory device increases, the pitch of the active regions 10 and 12 becomes small, and the word lines WL bent in the source strapping region SR may cause degradation of adjacent cell transistors. Therefore, as illustrated in FIGS. 1A and 1B, as the pitch of a cell array becomes small, an active region 12 passing the source strapping region SR may be wider in comparison with other active regions 10. The wider active region 12 can reduce or prevent a cell transistor adjacent to the source strapping region SR from being degraded.
An entire surface of a substrate including the word lines WL is covered with an interlayer dielectric layer 18. The drain contact BC penetrates the interlayer dielectric layer 18 to thereby connect to the drain region 16. The common source line CSL is formed by an impurity region implanted into an active region between the word lines where the device isolation layer is removed. A plurality of bit lines BL and source strapping lines SSL are formed crossing over the word lines WL on the interlayer dielectric layer in response to each of the active regions 10. The bit lines BL are connected to a drain contact BC, and the source strapping line SSL is connected to a source contact SC.